Figure 1. Block diagram of the direct digital synthesiser system.
Résumé Cet article traite d'une étude consacrée à l'utilisation des techniques de conformation du bruit et de compression des données appliquées à une table de sinus, en vue d'améliorer les performances d'un synthétiseur de fréquences numérique à synth se directe. Les algorithmes ont été vérifiés par modélisation numérique. Une maquette à base de réseaux logiques programmables par l'utilisateur a été conçue par ordinateur, puis fabriquée et testée. Les résultats des mesures sont présentés dans l'article.
Direct digital synthesis (DDS) is becoming increasingly popular as a technique for frequency synthesis, especially if high frequency resolution and fast switching between frequencies over a large bandwidth are required. Limiting factors are the spurious frequencies generated by this technique and the rather low output frequency. The latter drawback can be overcome by storing compressed data in ROM and this was studied. An important problem was maintaining the level of spurious outputs to those obtained with uncompressed data. Noise-shaping can be used to reduce the level of the spurious discrete frequency components caused by phase and amplitude truncation. However this technique cannot be universally applied to extend the spurious-free dynamic range of all frequencies generated.
Suppose that the instantaneous phase of a sinusoidal signal is given by a number stored in a digital accumulator. If the accumulator is incremented by adding a constant amount at each clock period, its content will represent a phase value which increases linearly with time. When the accumulator exceeds a value equivalent to 2pi radians, it overflows, multiples of 2pi are discarded, and the incrementation process continues to the next cycle. The number held in the accumulator is used to address a look-up table held in ROM (read- only memory) which converts phase information to a series of discrete, digitised samples of the amplitude of a sine-wave. A DAC (digital-to-analogue converter), followed by a low-pass filter, convert the digital samples into an analogue signal (Figure 1).
Figure 1. Block diagram of the direct digital synthesiser system.
There are mainly four sources of spurious products in a DDS:
A further limitation, due to Nyquist's sampling theorem, requires the maximum output frequency to be less than half the clock frequency. Synthesiser design is thus a trade-off between having a large, spurious-free, dynamic range and having a high speed, the former requiring reduced phase truncation, gained at the expense of a large, slow, ROM. The digital parts of the circuit are generally designed with a resolution small enough that the spurious-free dynamic range is determined by the properties of the DAC.
There are two aspects of noise-shaping:
It has been shown by simulation and measurement that there are frequencies for which noise-shaping brings no advantage or even deteriorates performance, and this technique cannot be generally used to improve the spurious free dynamic range in all cases.
The ROM is a bottleneck for high frequency performance since its functions cannot be pipelined to increase the sampling rate. The data held in ROM was compressed by interpolation techniques which exploit the symmetry between the quadrants of a sinusoid. By appropriately inverting the phase and amplitude of the sine-wave output, the look-up table need only hold information for phase values between 0 and pi/2.
The look-up table may be further reduced in size by dividing the phase table into coarse and fine segments, and storing values of the sine-wave after subtraction of the linear component, the dynamic range of the stored amplitude may be reduced. These techniques significantly reduce the data stored in ROM and largely replace them by arithmetic operations, which can be easily pipelined.
A prototype DDS, employing a 12-bit address width was built; this had a 74 dB spurious-free dynamic range and a ROM compression factor of 64, which was high enough to allow the ROM to be implemented in field-programable gate array (FPGA) using standard logic gates.
A DDS, using a 24-bit accumulator, and a compressed' ROM, using only 12-bit address word and giving an 11-bit output, was modelled in VHDL (very high speed integrated circuit hardware description language). After verification against the Matlab model, the FPGA netlist was synthesised using logic synthesis tools procured from Synopsys in combination with the FPGA library supplied by Actel.
Since the ROM compression technique and the noise shaping algorithms were independent of the clock speed, a clock frequency of 5 MHz was chosen to simplify the design of the FPGA. ROM output was available in two's-complement and in binary-offset format to allow various commercially available DACs to be used; for this a type 1280A FPGA by Actel was chosen, and the design was implemented using the company's proprietary ALS system.
The design included different test-modes to permit the effects of phase- and amplitude-truncation and noise-shaping at different locations inside the DDS to be studied in detail. A breadboard (Figure 2) was built, using the DDS on the FPGA, a type CLC912 DAC from Comlinear and a custom designed filter, from Allen Avionics, which had a 2 MHz cut-off frequency and an 80 dB attenuation at the Nyquist-frequency. A number of switches allowed the frequency word, phase offset and the different test modes to be preset.
Figure 2. The breadboard direct digital synthesiser.
Measurements made on the breadboard in its nominal operating mode confirmed the expected 70 dB spurious- free dynamic range, which was the limit for the DAC at this frequency. The feasibility of the ROM compression technique was verified. Subsequent tests were performed using the different test-modes to study, in more detail, noise-shaping at different frequencies. Test-modes allowed the outputs at spurious frequencies to be increased to a value above the noise floor of the DAC by truncating the phase value to 7 bits, thereby simplifying display on a spectrum analyser. Figure 3, compares the output spectra, measured with and without noise-shaping. Figure 3(a) shows the improvement due to both properties of the noise-shaper, de-correlation and shaping of the quantisation noise for an over-sampling system. Improvements shown in Figure 3(b) are mainly due to de-correlation and Figure 3(c) shows results for a frequency at which noise-shaping provides no improvement and even a slight deterioration.
(a)
(b)
(c)
Figure 3. Output spectra with and without noise shaping (see
text).
A look-up table compression technique has been successfully implemented to increase the sampling-rate of a DDS without degrading the spurious-free dynamic range. The reduction of spurious frequencies by the use of new algorithms which remove the short-comings of the noise-shaping technique is now being studied. These algorithms, together with the ROM compression technique, will be implemented, with increased bandwidth, in a gallium arsenide device.
Preparing for the Future Vol. 6 No. 2