Figure 1. Circuit diagrams of NOR gates. (a) DCFL and (b) BDCFL
Digital circuitry will continue to increase its presence in future Earth observation and communications systems. Research now emphasises the use of digital signal processing in place of analogue baseband processing, and studies are now being prepared to replace analogue processing at frequencies of several hundred megahertz by digital techniques.
To evaluate the capability of gallium arsenide integrated circuits, three different frequency divider chips have been designed at ESTEC and manufactured by Philips Microwave Limeil (F) using their prorietary ER07AD process. These divide-by-eight circuits are intended as prescalers in phase-lock loops, in which they divide the frequency of a voltage-controlled oscillator down to a lower frequency at which phase comparison with an accurate reference takes place. The dividers have power-speed products which make them ideal for microwave applications.
The ER07AD process is intended for applications requiring mixed analog and digital circuitry of low complexity. The process is based on an enhancement-mode MESFET (metal-semiconductor field effect transistor) which has a 0.7 micron gate length, a 17 GHz transit frequency, and a threshold voltage of 175 mV. Since the process is not self- aligned, its yield is low and device complexity is limited to about two thousand transistors per chip.
To facilitate circuit design, PML can provide a large-signal model, based on the Curtice quadratic model, which has been optimised for speed and guaranteed convergence, at the expense of simplifying the way variations in transistor parameters with operating point are handled. These limitations hinder a realistic simulation of the gain and loading of a cell, which prevents the designer from exploiting the ultimate performance of the process.
In designing logic circuits at transistor level, not only must the configuration of the logic gates be defined, but also the static and dynamic characteristics of the gates must ensure proper operation under worst case conditions. In addition the chip area used by the circuit and parasitic effects must both be minimised.
The optimisation of logic gates consists of determining the best trade off between design parameters such as speed, noise margin, fan-in and fan-out and power consumption. Gallium arsenide gates are usually optimised for high speed, obtained at the expense of reduced gain and noise margin.
Many different logic families exist. Of these, the three most important, DCFL (direct coupled field effect transistor Logic), BDCFL) (buffered DCFL) and W-OR-NOR (wired-or-nor), were evaluated for implementing a circuit to divide the frequency of an input signal by eight. These families provide static logic; implementation in dynamic logic, in which data is represented by stored charge, is difficult to do in gallium arsenide due to high gate leakage, and the need to prevent forward biasing the gate. Only enhancement type MESFETs are used and only one power supply is required. As there are no complementary MESFETs, only ratioed logic gates can be used, and this requires well defined logical-low and -high levels which are obtained from the gate transfer curve. The gate threshold is usually placed in the mid-point of the logic swing to maximise the noise margin.
Test circuits were implemented using resistive loads, as the threshold voltage of the available depletion-mode MESFET was unsuitable. Future depletion mode devices are expected to be suitable for use as active loads. For all three designs, emphasis was placed on achieving high speed with low power consumption, and NOR structures were used, since these are faster. The results of this work are summarised in Table 1.
DCFL BDCFL Wired OR-NOR _________________________________________________ Max. Freq. 1.5 GHz 1.9 Ghz 3.0 Ghz Power Cons. 48mW 59Mw 70Mw MESFETs 45 63 39 Resistors 21 39 48
DCFL gates have the advantages of simplicity and very few circuit elements per gate (Figure 1(a)). This results in higher function density and lower power consumption and fewer parasitic elements caused by interconnections.
The logical low level is set at zero volts, sufficient to pinch off the succeeding gate; the logical high level is limited by the barrier height of the gate diode (0.7 V). As a consequence, DCFL circuits have a relatively small voltage swing and low noise margin. Stringent requirements on the doping and thickness of the active layer, needed to maintain a uniform threshold voltage across the whole chip, make processing difficult. Figure 2(a) shows the gate transfer curve. Figure 3(a) shows the basic divide-by-two cell.
Adding a buffer stage to a DCFL circuit gives a BDCFL gate (Figure 1(b)). The buffer gives higher noise immunity, increased speed under high loading and reduced sensitivity to fan-out and large capacitive loads. Its main disadvantages are increased power consumption and complexity.
Figure 2(b) shows the transfer curve of a BDCFL gate.
A basic edge-triggered flip-flop is implemented in DCFL using six NOR gates (Figure 3(a)). When used to divide-by-two, the circuit suffers a delay equal to four gate-delays. The maximum input frequency cannot exceed 1/(4t), where t is one gate-delay time.
Using a wired-OR-NOR configuration, the delay of a latch can be reduced to a single gate delay, allowing a master-slave flip-flop a maximum frequency of 1/(2t) to be realised. However this arrangement requires two complementary non-overlapping clock signals, making it very sensitive to timing skew between the two clock signals.
The transistor diagram of the basic wired-OR-NOR cell is shown in Figure 3(d). The logic diagram of a basic divide-by-two circuit, implemented using four basic cells, is shown in Figure 3(c). The complete divide-by-eight consists of three divide-by-two cells in cascade, supplemented by two output-buffers which drive the 50 Ohm load and a complementary clock generator (Figure 3(b)). The layout of the complete divide-by-eight scaler is shown in Figure 4.
Figure 1. Circuit diagrams of NOR gates. (a) DCFL and (b) BDCFL
Figure 2. Gate Transfer curve (a) DCFL and (b) BDCFL
Figure 3. (a) Basic divide-by-two circuit; (b) Complementary clock generator; (c) basic divide-by-two cell in Wired-OR-NOR logic; (d) circuit topology of a wired-OR-NOR cell
Figure 4. Layout of a divide-by-8 circuit designed using wired-OR-NOR cells
The various test circuits were mounted on alumina substrates and placed on kovar carrier in a test jig. Signals were input and output using miniature SMA-type coaxial connectors. Test equipment comprised sine wave generator, an oscilloscope and a microwave frequency counter. Measurements of the maximum input frequencies are given in Table 1. Power consumption figures include power drawn by output buffers. Figure 5 shows waveform measurements on the counter implemented in BDCFL.
The maximum frequency measured for the wired-OR-NOR divider was 3 GHz, which was lower than predicted by the simulator. As proper extraction software was not available for back-annotating the parasitic elements in the layout, it was not possible to optimise the skew bet-ween phases of the two clocks, to which this type of circuit is very sensitive.
Figure 5. Waveform measurements on a BDCFL counter
Three different circuit topologies, wired-OR-NOR, BDCFL and DCFL, have been used to implement a high-speed divide-by-eight circuit using gallium arsenide MESFETs. The fastest of these was the wired-OR-NOR whose maximum clock frequency was 3 GHz. The other topologies gave maximum clock frequencies of 1.9 and 1.5 GHz with corresponding reductions in power consumption.
Preparing for the Future Vol. 5 No. 2.